In many applications, including digital communications, clock and data recovery (CDR) must be performed before data can be decoded. Generally, in a digital clock recovery system, timing information is extracted from the input serial data stream and a reference clock signal of a given frequency is generated, together with a number of different clock signals having the same frequency but with different phases. In one typical implementation, the different clock signals are generated by applying the reference clock signal to a delay network. Thereafter, one or more of the clock signals are compared to the phase and frequency of an incoming data stream and one or more of the clock signals are selected for data recovery.
FIG. 1 illustrates the transitions of a data stream histogram 100 for a given unit interval. As shown in FIG. 1, the data is “ideally” sampled in the middle of the unit interval between two transition points. The phases generated by the CDR system are adjusted to align with the transitions and sample points, respectively. Thus, the internal clock is typically delayed so that the data sampling is adjusted to the center of the “data eye,” in a known manner. Such uniformly spaced transition and data sampling clock phases are generally considered useful under “ideal” circumstances.
The duty cycle of a clock signal can be expressed as the ratio of all pulse durations to the total period. A clock should typically demonstrate a 50% duty cycle. Duty cycle distortion arises, for example, due to mismatches in the clock buffers that are required to drive these clock phases, and due to variations in the different signal paths for clock and data. The target 50% duty cycle feature is particularly important for high-speed applications where both positive and negative edges are used. Thus, a trimming technique is often performed for the clock buffers to compensate for the mismatch, so that the sampling phases can be equally spaced.
A number of techniques have been proposed for the trimming of clock buffers. Existing techniques, however, often use a reference clock to trim the different clock signals. Any duty cycle distortion in the reference clock directly and negatively influences the performance of the clock trim operation. A need therefore exists for improved techniques for the trimming of clock buffers.